A simple CPU board handles all data sampling and control.

A temperature compensated crystal osc provides the CPU clock and is used as the timebase for data sampling. The osc is divided down to provide a clock at the basic 20 sec data sample period. The 20 sec clock is used to wake the CPU from powerdown mode. The CPU wakes up, samples data, saves it in a SRAM memory buffer and goes back to sleep.

When the CPU detects a magnetic field sample with magnitude above some threshold it switches to transmit mode. The transmitter power is turned on, data is formatted and written from the SRAM data buffer to the transmitter bitstream. The data buffer is dumped repeatedly for the duration of transmit mode (about 10 minutes). The transmit power is turned off and the CPU goes back to sampling data at 20 sec intervals.

Part Selection

An 80C186 seems a reasonable choice since it is available in rad hard and should be adequate for the simple processing needs. A slower clock speed could be used to cut power since processing needs are so low.The most effective way to save power is to use the powerdown feature to duty cycle. In this case the clock speed doesn't change the average much (if it is clocked twice as fast it uses twice as much power while on but gets done in half the time). Higher speeds give good timing resolution for the sun sensor pulse and generally make direct control of peripherals easier. An 80C186 CPU should have enough I/O bits to directly control the few peripherals with little or no glue logic.

80C186 5V power 63mA@12MHz 100uA powerdown mode.

The SRAM memory is sized to save 2 orbits worth of data. The oldest orbit data is replaced on the next orbit. This allows the downlink to miss one pass without any data loss. One sample every 20 second for the longest orbit of 3 days. 3days*24hrs*3600sec/20 * 3 axis * 2bytes = 78K bytes/orbit. Housekeeping and other data would add another 30% to bring it up to about 100 Kbytes/orbit. A 256Kbyte memory might be adequate for 2 orbits. It might be nice to save more information per sample to help with despin of the mag vector. Depending on what is available for rad hard chips it might be better to bump it up to a 512Kbyte buffer. For a 12Mhz CPU, 100ns access or even a bit slower would be adequate.

Possible: UTMC UT7Q512 512Kx8 SRAM 100ns 55mA active 1mA standby.

The program memory can be PROM, EPROM, EEPROM, FLASH or whatever is available in rad hard. There isn't a real need for in flight re-programming. The 64Kbyte size is mostly a guess at this point. The processing needs are pretty minimal. Again 100ns access or even a bit slower would be adequate. A low current standby mode is important.

Possible: UTMC UT28F256 Rad hard 32KX8 PROM 45ns 20mA active 2mA standby.

A simple ADC with 8 or 16 inputs, 8-bit resolution and slow conversion times can handle all the houskeeping monitor functions. There are many single chip solutions. Rad-hard versions might be hard to find.

Temperature sensors and a couple micro-power op-amps should be the only other components needed for housekeeping functions.

Sun sensor pulse timing can be handled by directly the CPU. The sensors require a simple threshold detector to convert the pulse to a logic level.

An external shift register may be needed to generate the bitstream for the transmitter. The reciever will presumably have a low bitrate and can probably be handled directly with I/O bits.