SERSIO UNH Interface Connectors 5/06/03 All interface to telemetry and power is through 37 pin D connectors. 37P connectors will be mounted on the UNH electronics boxes. Wallops will supply mating 37S connectors on cables. Most signals are wired as twisted pairs. The pinout lists give the signal pin and show its pair pin in parenthesis. Some low rate analog monitors are single wires so no return pair is shown. For PCM signals the + and - differential lines are twisted together. The - pin is NOT ground. Independent pairs should be carried through to the final destination. All power returns should be wired independently to power ground. Analog signal returns may be tied together at a ground buss near their destination. Returns marked with a * are optional and can be left out of the flight cable as long the signal has a return path via power or analog return. The single wire "chassis" pin is intended as a redundant means of insuring a good electrical connection between the experiment chassis and the TM section chassis. This pin may be tied to chassis in the TM section wherever it is convenient. The main payload has 3 UNH interface conectors. Box 1 (BEEPS & HT2) 37 pin D connector (37S on cable) SIG RET 1 (20) +28V power 2 (21) +28V power 3 (22)* HVTO High Voltage Turn On 4 (23)* TEST Pulse amp test + - 5 (24) MAJF PCM major frame sync 6 (25) GCKT2 Gated shift clock for HEEPS T2 7 (26) HT2I HEEPS T2 image serial data 8 (27) HT2T HEEPS T2 total counts 9 (28) GCKP Gated shift clock for BEEPS P 10 (29) GCKO Gated shift clock for BEEPS O 11 (30) BPI BEEPS P image serial data 12 (31) BOI BEEPS O image serial data 13 (32) BPT BEEPS P total counts 14 (33) BOT BEEPS O total counts SIG RET 15 (34) BS BEEPS sweep monitor 16 (35)* BB BEEPS HT2 bias monitor 17 (36) HT2S HEEPS T2 sweep 18 BC BEEPS box current 19 HP HEEPS skin potential 37 chassis Box 2 (HE & TED) 37 pin D connector (37S on cable) SIG RET 1 (20) +28V power 2 (21) +28V power 3 (22)* HVTO High Voltage Turn On 4 (23)* TEST Pulse amp test + - 5 (24) MAJF PCM major frame sync 6 (25) GCKE Gated shift clock for HEEPS E 7 (26) HEI HEEPS E image serial data 8 (27) HET HEEPS E total counts 9 (28) TED1 TED1 total counts 10 (29) TED2 TED2 total counts SIG RET 11 (30) TS TED sweep monitor 12 (31)* TP TED skin potential 13 (32)* TB TED bias monitor 14 (33) 15 (34) HES HEEPS E sweep monitor 16 (35)* HEB HEEPS E bias monitor 17 (36)* HEC HEEPS E box current 18 19 37 chassis Box 3 (HH HM HT1) 37 pin D connector (37S on cable) SIG RET 1 (20) +28V power 2 (21) +28V power 3 (22)* HVTO High Voltage Turn On 4 (23)* TEST Pulse amp test + - 5 (24) MAJF PCM major frame sync 6 (25) GCKT1 Gated shift clock for HEEPS T1 7 (26) HT1I HEEPS T1 image serial data 8 (27) HT1T HEEPS T1 total counts 9 (28) GCKM Gated shift clock for HEEPS M 10 (29) HMI HEEPS M image serial data 11 (30) HMT HEEPS M total counts 12 (31) HH1 H pad 1 counts 13 (32) HH2 H pad 2 counts 14 (33) HH3 H pad 3 counts 15 (34) HH4 H pad 4 counts SIG RET 16 (35) HMS HEEPS M sweep monitor 17 HHS HEEPS H sweep monitor 18 HT1S HEEPS T1 sweep monitor 19 HHB HEEPS H M T1 bias monitor 36 HHC HH box current 37 chassis Subpayload ERPA box 9 pin D connector (9S on cable) SIG RET 1 (6) +28V power + - 2 (7) MAJF PCM major frame sync 3 (8) GCKR Gated shift clock ERPA 4 (9) RSD ERPA serial data 5