The basic plan is to use a 80C552 microcontroller board and a small amount of glue logic to take data with the ASIC. The microcontroller includes an 8-chan 10-bit ADC, several I/O bits, 32Kbyte memory and a RS232 serial port. Firmware is uploaded to the 80C552. Event data is saved in the onboard memory and then transfered via RS232 to a controlling computer.
The current plan is to support 4 chips for a total of 16 pixels. Each ASIC socket will have the associated bias resistors, an output opamp and a shift register for the pixel enable bits. (see ASIC socket schematic 6-18-01).
An off chip amp is used to provide gain and offset that converts the signal to an approximately 0 to 3V range for the CPU's ADC. An LT1784 is a low voltage low power amp that may be similar to something that could be done on chip. (Although an on chip ADC may get by with a smaller range).
An off chip shift register is used to set up the pixel enable bits. Presumably it would be straight forward to move this on chip in future versions. The shift registers for each ASIC is daisy chained with the next so that the CPU loads all bits as one long serial word.
Most of the control voltages and logic signals are wired in common to all 4 chips. The support logic that interfaces to the CPU I/O bits to generate these signals is shown in the support logic schematic.
An octal DAC provides for program control of 8 different analog voltages. The DAC outputs control shaping constants, thresholds, and ADC fullscale and zero.
An external circuit provides the timing for the trigger sample/hold. The CPU can vary the trigger to hold delay.
The CPU is run at 5V. All output bits go through 74VHC chips with 5V tolerant inputs to convert them to 3.3V levels for the ASIC. The ASIC input pads may in fact be 5V tolerant but it is probably better to test with 3.3V levels. The ASIC read discriminator outputs (dav) are fed directly to the CPU which has a logic input hi spec of 1.9V. Presumaby these outputs will pull up to better than 1.9V under no load.
To keep the readout process as fast as possible, some of the reset signals are derived rather than being directly under CPU control. Readout enable (ren) is a delayed and inverted copy of the readout reset (reset3). This means that reset is released 100ns before the enable. On the trailing edge (after the value is converted) reset will activate before the enable is released. This shouldn't hurt anything but it is different from the timing shown in previous documentation.
Resets for the preamp stages (reset1 and reset2) probably will not be needed at all but some circuitry is included to provide the option of a 140ns pulse at the rise of the DONE control bit. This control bit is pulsed by the CPU to clear an event after all pixels have been read out.
The power requirements are expected to be very low so a separate low power linear regulator is used on board for both the +5V and +3.3V supply. The CPU board will have its own 5V regulator. This should provide good rejection of any noise generated by the CPU. The 3.3V supply to the preamp stages is filtered at each ASIC to (hopefully) keep any remaining noise out of the preamp.