The shape of the waveform at the input to the sample/hold was re-created by varying the delay from the test pulse edge to the hold signal. A pulse height distribution was taken at each delay.
The 4 traces are from the 4 different channels on the ASIC. The lowest trace is from channel 3 which is the one with the spy outputs. The next lowest one is channel 0. Its lower signal may be due to a lower capacitance between this input pin and the test pulse. The pin to pin capacitance of the package and socket probably contribute more than the 0.1pF on-chip capacitance. All channels except channel 0 have two adjacent pins with the test pulse on them.
This data was taken with trigo (the open drain trigger OR output pin) disconnected. The trigo pin apparently has some coupling into the signal path. When the externally generated trigger signal is connected to this pin (as it should be), there is a significant signal seen at the sample/hold even when the test pulse is disconnected. With the external trigger signal disconnected from the ASIC pin there is much less shift seen in the zero level.
Setup:
puadj = 3.0
sh1adj = 1.5
preadj = 1.9
th1adj = 3.0 30K (disable disc 1)
th2adj = 1.9 (convert all)
zeroadj = 0.9
fullscale = 3.0