The test board allows computer control of some of the adjust voltages for the ASIC. It is possible to sweep one adjustment while keeping the others constant and look at the resulting pulse height distributions. This gives some idea of the effect of the control but the controls interact and change several aspects of the performance at once.
The following plots were all done with a single pixel APD under 1700V bias. This corresponds to about 80nA leakage current.
With leakage current present, the preadj voltage must be above 1.4V to get any pulse response. The zero level remains nearly constant.
The sh1adj voltage causes a sharp transition in the zero level above 1.7V. This happens only when there is leakage curent and the amount of zero shift is dependent on the amount of leakage current.
The puadj voltage seems to have little effect on anything other than the zero level. The zero level moves outside the range of the external adc for this setup but lower values of puadj could be used by changing the adc zero.
All of the above sweeps were done with the delay set at 550ns. This is the peak for the default setup values.
